1. Field of the Invention
This invention relates to tools for analysis of a split-transaction bus and more particularly to an intelligent decoder that interprets bus protocols and associates request packets and response packets on a split-transaction bus.
2. Description of the Related Art
Logic analyzers have been used for years to help debug and evaluate electronic circuits. Typically, probes or connectors are attached to signals on an electronic circuit, for example, a printed circuit board (PCB). The activities of the signals are monitored and displayed on a logic analyzer's screen or computer screen as waveforms and/or as logic levels. A user interface is typically used to define signal names with the option of grouping and displaying signals as a bus. A logic analyzer can provide features such as triggering on the occurrence of certain logic levels of the signals, the occurrence of bus transactions such as a write operation to a specific address and other such things. Upon the occurrence of a trigger condition, an amount of the signals' activities are stored and displayed on a display screen for interpretation by the user. The user can spend many hours manually deciphering data and waveforms.
For very complex busses, instead of manually deciphering the bus and its transactions, another technique can be used. For example, after a trigger condition a logic analyzer can store all bus signal activity in memory for a specific amount of time. Then, a software tool is used to post-process the data. For example, the software tool can group the signal transitions into bus transactions and present a display or printout of the signal activities in a more complex and comprehensive form. However, because the data is stored and later post-processed, the analysis is not a real time solution and typically doesn't allow real-time triggering on complex events.
Some logic analyzers do provide bus support, for example, a logic analyzer can provide support for a specific bus, for example, the PCI bus. Signal naming and grouping can be automated, probes are specific to the particular type of bus, protocol decoding can be provided, and bus-specific triggering can be provided. However, these logic analyzers typically only monitor a bus and decode the signals according to the bus protocol, for example, converting a 32-bit value into a command or address.
While providing this type of specific bus support is valuable and makes analysis of an electronic circuit easier, more complicated busses and transactions are not supported. For example, support for a split-transaction bus, in which responses are separate from a corresponding request, requires more sophisticated analysis. A traditional logic analyzer probing a split-transaction bus, for example, a HyperTransport™ (HT) link, has no straightforward way to trigger on a read request and its associated response. The traditional logic analysis method would buffer the split-transaction bus traffic and then post-process the buffered data to identify the desired packets. Additionally, if the split-transaction bus uses an address in a request packet, and uses a tag instead of the address in a response packet, address translation is required. Post-processing is typically used to analyze a split-transaction bus. However, this does not provide real time analysis capability and thus triggering on specific events is unavailable.
As busses become more complex and high-speed, a real-time intelligent split-transaction bus decoder is needed.